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september 1997 1-389 ? 1997 actel corporation actel mask programmed gate arrays features ? mask programmed versions of actel field programmable gate arrays (fpgas) ? significant cost reduction for medium- to high-volume applications ? pin-for-pin compatible with actel fpgas ? pci local bus revision 2 compliant ? automatic translation from actel fpga netlist to mpga ? test vectors generated from customer simulation vectors ? short lead times for prototype and production devices ? mpga available for all act 1, act 2, 1200xl, act 3, and 3200dx devices ? device sizes from 1,200 to 10,000 gates ? up to 175 user i/os ? available in commercial or industrial temperature ranges ? plcc, pqfp, vqfp, and tqfp packages available ? meets all internal worst-case fpga performance specifications ? lower i/o capacitance than fpga ? lower power dissipation than fpga description the actel mask programmed gate array (mpga) products are masked versions of the popular actel fpga families. these semi-custom devices offer the customer a design path that provides significant cost reduction without significant risk or engineering effort. for medium- to high-volume applications in which the design is fixed, the actel fpga used for prototyping and initial production can be replaced by the corresponding mpga device. product family profile capacity available packages mpga device type gate array equivalent gates pld equivalent gates flip-flops (maximum) user i/os (maximum) plcc pqfp vqfp tqfp m1010 1,200 3,000 147 57 44, 68-pin 100-pin 80-pin m1020 2,000 6,000 273 69 44, 68, 84-pin 100-pin 80-pin m1225 2,500 6,250 382 83 84-pin 100-pin 100-pin m1240 4,000 10,000 568 104 84-pin 100, 144-pin 176-pin m1280 8,000 20,000 998 140 84-pin 100, 160, 208-pin 176-pin m1415 1,500 3,750 312 80 84-pin 100-pin 100-pin m1425 2,500 6,250 435 100 84-pin 100, 160-pin 100-pin m1440 4,000 10,000 706 140 84-pin 160-pin 100-pin 176-pin m1460 6,000 15,000 976 167 160, 208-pin 176-pin m14100 10,000 25,000 1153 175 208-pin m3265 6,500 1,600 747 126 84-pin 100, 160-pin 176-pin m32100 10,000 25,000 1031 152 84-pin 160, 208-pin 176-pin m32140 14,000 35,000 1410 176 84-pin 160, 208-pin 176-pin m32200 20,000 50,000 1822 202 208, 240-pin m32300 30,000 75,000 2804 250 208, 240-pin m32400 40,000 100,000 3759 288 240-pin
1- 390 the granular, regular structure of the actel antifuse-based fpga products enables easy conversion to mpga. actel provides all required engineering services to convert the customer design from fpga to mpga, using proprietary software to automatically convert the fpga logic design into the mpga device. test vector generation is made easy by software that converts the customer's third- party simulation vectors into the final vectors used to test the device in production. all actel mpga devices are pin-for-pin compatible with the corresponding fpga, and therefore no board redesign is required. mpga devices meet all worst- case timing specifications of the fpga devices. mpga devices are available for all plastic packaged devices from act 1, act 2, 1200xl, act 3, and 3200dx families. see the product plan on page 1-260 for a detailed list of available device and package combinations. actel fpga to mpga design flow actels three families of fpga devices offer a wide selection of device sizes, package choices, performance characteristics, and price points. the fpga families provide the ideal prototyping tool and are cost-effective for low- to medium- volume applications. as volumes increase, a cost- reduction path becomes a key factor to ensure continued success and profitability of the end product. once the design has stabilized and volumes are increasing, a choice can be made to convert the design to an mpga. since the mpga product is pin-for-pin compatible with the fpga, no board redesign is required, and the mpga can directly replace the fpga. a typical design process uses the fpga device as the prototyping and initial production product of choice and converts to the mpga as volumes warrant. figure 1 shows the design process for actel fpga and mpga devices. this option gives you the flexibility to adjust volumes as the demand for the end product changes. since the mpga is a semicustom device, all production is built to your order. if the design is already completed in the fpga, any demand upsides can be satisfied by temporarily switching production back to the fpga. since actel fpgas are standard off-the-shelf devices, additional product requirements can be met within a short lead time. the actel fpga devices offer the easiest and fastest way to bring a new product to market, and the three fpga families offer a wide selection of low-cost, high-performance devices. the addition of the mpga devices offers a simple, low-risk cost- reduction path as production volumes increase.
1- 391 actel mask programmed gate arrays figure 1 ? actel device design flow cae t ools design entr y sim ulation netlist designer/designer adv antage system ? a ctmap fpga fitter ? a ctgen macro builder ? a uto place and route ? chipedit ? timer ? bac kannotation fpga prog r ammers ? activ ator 2 ? activ ator 2s ? data i/o unisite , 3900 a utosite actel mpga t ools ? sim ulation ? timing analysis ? p o w er calculation design star t chec klist mpga bac k-annotation (optional) actel fpga de vices actel mpga prototype de vices de vice t est in- system t est prototype appro v al final re vie w actel mpga production de vices fpga design flo w mpga design flo w (note: shaded items are completed b y the customer .) sim ulation v ectors
1- 392 product plan a v ailability application a ct 1 f amil y commer cial industrial m1010 de vice 44-pin plastic leaded chip carr ier (plcc) 68-pin plastic leaded chip carr ier (plcc) 80-pin v er y thin plastic quad flatpac k (vqfp) 100-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 4 4 4 4 4 4 m1020 de vice 44-pin plastic leaded chip carr ier (plcc) 68-pin plastic leaded chip carr ier (plcc) 80-pin v er y thin plastic quad flatpac k (vqfp) 84-pin plastic leaded chip carr ier (plcc) 100-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 a ct 2/1200xl f amil y m1225 de vice 84-pin plastic leaded chip carr ier (plcc) 100-pin plastic quad flatpac k (pqfp) 100-pin thin plastic quad flatpac k (tqfp) 4 4 4 4 4 4 4 4 m1240 de vice 84-pin plastic leaded chip carr ier (plcc) 100-pin plastic quad flatpac k (pqfp) 144-pin plastic quad flatpac k (pqfp) 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 4 4 4 4 4 4 4 4 m1280 de vice 84-pin plastic leaded chip carr ier (plcc) 100-pin plastic quad flatpac k (pqfp) 160-pin plastic quad flatpac k (pqfp) 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 4 4 4 4 4 4 4 4 a ct 3 f amil y m1415 de vice 84-pin plastic leaded chip carr ier (plcc) 100-pin plastic quad flatpac k (pqfp) 100-pin v er y thin plastic quad flatpac k (vqfp) 4 4 4 4 4 4 4 4 note: m1425 device 84-pin plastic leaded chip carr ier (plcc) 100-pin plastic quad flatpac k (pqfp) 100-pin v er y thin plastic quad flatpac k (vqfp) 160-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 4 4 4 4 4 4 m1440 de vice 84-pin plastic leaded chip carr ier (plcc) 100-pin v er y thin plastic quad flatpac k (vqfp) 160-pin plastic quad flatpac k (pqfp) 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 4 4 4 4 4 4 4 m1460 de vice 160-pin plastic quad flatpac k (pqfp) 176-pin thin plastic quad flatpac k (tqfp) 208-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 4 4 4 m14100 de vice 208-pin plastic quad flatpac k (pqfp) 4 4 4
1- 393 actel mask programmed gate arrays act 1 device resources act 2/1200xl device resources 3200dx f amil y m3265 de vice 84-pin plastic leaded chip carr ier (plcc) 100-pin plastic quad flatpac k (pqfp) 160-pin plastic quad flatpac k (pqfp) 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 4 4 4 4 4 4 4 4 4 m32100 de vice 84-pin plastic leaded chip carr ier (plcc) 160-pin plastic quad flatpac k (pqfp) 208-pin plastic quad flatpac k (pqfp) 176-pin thin plastic quad flatpac k (tqfp) p p p p p p p p p p p p m32140 de vice 84-pin plastic leaded chip carr ier (plcc) 160-pin plastic quad flatpac k (pqfp) 208-pin plastic quad flatpac k (pqfp) 176-pin thin plastic quad flatpac k (tqfp) 4 4 4 4 4 4 4 4 4 4 4 4 m32200 de vice 208-pin plastic quad flatpac k (pqfp) 240-pin plastic quad flatpac k (pqfp) 176-pin this plastic quad flatpac k (tqfp) 4 4 4 4 4 4 4 4 4 m32300 de vice 208-pin plastic quad flatpac k (pqfp) 240-pin plastic quad flatpac k (pqfp) 4 4 4 4 4 4 a v ailability: 4 = a v ailab le p = planned = not planned mpga de vice t ype gate arra y equiv alent gates user i/os plcc pqfp vqfp 44-pin 68-pin 84-pin 100-pin 80-pin m1010 1200 34 57 57 57 57 m1020 2000 34 57 69 69 69 product plan (continued) a v ailability application mpga de vice t ype gate arra y equiv alent gates user i/os plcc pqfp vqfp tqfp 84-pin 100-pin 144-pin 160-pin 208-pin 100-pin 176-pin m1225 2500 72 83 83 m1240 4000 72 83 104 104 m1280 8000 72 83 125 140 140
1- 394 act 3 device resources 3200dx device resources ordering information mpga de vice t ype gate arra y equiv alent gates user i/os plcc pqfp vqfp tqfp 84-pin 100-pin 160-pin 208-pin 100-pin 176-pin m1415 1500 70 80 80 m1425 2500 70 80 100 83 m1440 4000 70 131 83 140 m1460 6000 131 167 151 m14100 10000 175 mpga de vice t ype gate arra y equiv alent gates user i/os plcc pqfp tqfp 84-pin 100-pin 160-pin 208-pin 240-pin 176-pin m3265 6500 72 83 125 126 m32100 10000 72 125 156 151 m32140 14000 72 125 176 151 m32200 20000 176 tbd m32300 30000 176 tbd m32400 40000 tbd application (t emper ature range) c = commercial (0 to +70 c) i = industr ial (C40 to +85 c) p ar t number m1010 = 1200 gatesa ct 1 m1020 = 2000 gatesa ct 1 m1225 = 2500 gatesa ct 2/1200xl m1240 = 4000 gatesa ct 2/1200xl m1280 = 8000 gatesa ct 2/1200xl m1415 = 1500 gatesa ct 3 m1425 = 2500 gatesa ct 3 m1440 = 4000 gatesa ct 3 m1460 = 6000 gatesa ct 3 m14100 = 10000 gatesa ct 3 m3265 = 6500 gates3200dx m32100 = 10000 gates3200dx m32140 = 14000 gates3200dx m32200 = 20000 gates3200dx m32300 = 30000 gates3200dx m32400 = 40000 gates3200dx p ac kage lead count m14100 C rq 208 c p ac kage t ype pl = plastic leaded chip carr ier (plcc) pq = plastic quad flatpac k (pqfp) tq = thin (1.4 mm) plastic quad flatpac k (tqfp) vq = v er y thin (1.0 mm) plastic quad flatpac k (vqfp) rq = p o w er plastic quad flatpac k (rqfp)
1- 395 actel mask programmed gate arrays absolute maximum ratings 1 recommended operating conditions electrical specifications free air temperature range symbol p arameter limits units v cc dc supply v oltage C0.3 to +7.0 v v i input v oltage C0.3 to v cc +0.3 v v o output v oltage C0.3 to v cc +0.3 v i io i/o source sink current 20 ma t stg stor age t emper ature C55 to +125 c note: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. p arameter commer cial industrial units t emper ature range 0 to +70 C40 to +85 c p o w er supply t oler ance 5 10 %v cc symbol p arameter t est condition commer cial industrial units min. max. min. max. v oh 1,2 high le v el output i oh = C6 ma (cmos) 3.7 3.7 v i oh = C8 ma (ttl) 3 2.4 2.4 v v ol 1,2 lo w le v el output i ol = +6 ma (cmos) 0.4 0.4 v i ol = +8 ma (ttl) 3 0.4 0.4 v v ih high le v el input ttl inputs 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il lo w le v el input ttl inputs C0.3 0.8 C0.3 0.8 v i in input leakage v i = v cc or gnd C1 +1 C1 +1 m a i oz 3-state output leakage v o = v cc or gnd C10 +10 C10 +10 m a c io i/o capacitance 3 10 10 pf i cc(s) standb y supply current v i = v cc or gnd , i o = 0 ma 100 500 m a notes: 1. actel devices can drive and receive either cmos or ttl signal levels. no assignment of i/os as ttl or cmos is required. 2. tested one output at a time, v cc = min. 3. not tested, for information only.
1- 396 chip-to-chip performance chip-to-chip p erf ormance (w or st- case commer cial) t (global clock t o ouput p ad) t tra ce t (input setup) t otal mhz actel mpga 12.7 1.0 3.1 16.8 60 35 pf clk clk t (global clock t tra ce t (input setup) chip #1 chip #2 t o output p ad) up to 1000 cloc k loads
1- 397 actel mask programmed gate arrays pin description package pin assignments for an fpga design are directly transferred to the equivalent mpga package because all i/o and power pins are located in identical positions. while the conversion of package pin assignments is transparent in the end product, there are two small functional differences to note between the device types. first, dedicated fpga global and debugging pins are general purpose mpga i/o pins. also, dedicated fpga programming voltage pins are vcc or ground pins on an mpga. refer to table 1 for a complete cross- reference of pin descriptions between the fpga and mpga. table 1 ? fpga-to-mpga pin cross- reference fpga pin description mpga pin description clk cloc k (a ct 1 onl y) ttl cloc k input f or a ct 1 global cloc k distr ib ution net- w or k. this pin can also be used as an i/o . ? no chang e if desired, ttl cloc k input signals ma y be mo v ed to an y mpga i/o location. clka cloc k a (a ct 3, 3200dx, 1200xl, and a ct 2 onl y) ttl cloc k input f or cloc k distr ib ution netw or ks . this pin can also be used as an i/o . ? no chang e if desired, ttl cloc k input signals ma y be mo v ed to an y mpga i/o location. clkb cloc k b (a ct 3, 3200dx, 1200xl, and a ct 2 onl y) ttl cloc k input f or cloc k distr ib ution netw or ks . this pin can also be used as an i/o . ? no chang e if desired, ttl cloc k input signals ma y be mo v ed to an y mpga i/o location. dclk dia gnostic cloc k ttl cloc k input f or diagnostic probe and de vice prog r am- ming. function is controlled b y the mode pin. ? i/o this pin is used as an i/o only . it is not used f or diagnos- tic probe or de vice prog r amming functions on an mpga. gnd gr ound lo w supply v oltage . ? gr ound lo w supply v oltage . hclk dedicated (har d-wired) arra y cloc k (a ct 3 onl y) ttl cloc k input f or a ct 3 sequential modules . this pin can also be used as an i/o . ? no chang e if desired, ttl cloc k input signals ma y be mo v ed to an y mpga i/o location. i/o input/output the i/o pin functions as an input, output, three-state , or bidirectional b uff er . un used pins are automatically dr iv en lo w b y the designer softw are . ? i/o user-de? ned mpga i/o pins function identically to their fpga counter par ts . ho w e v er , un used pins are nc (no connection) pins . ioclk dedicated (har d-wired) i/o cloc k (a ct 3 onl y) ttl cloc k input f or a ct 3 i/o modules . this pin can also be used as an i/o . ? no chang e if desired, ttl cloc k input signals ma y be mo v ed to an y mpga i/o location. iopcl dedicated (har d-wired) i/o preset/clear (a ct 3 onl y) ttl input f or a ct 3 i/o preset or clear . this pin can also be used as an i/o . ? no chang e if desired, this input signal ma y be mo v ed to an y mpga i/o location. mode mode the mode pin controls the use of diagnostic pins (dclk, pra, prb , sdi). when the mode pin is high, the spe- cial functions are activ e . when the mode pin is lo w , the pins function as i/os . ? test (no connection) this pin is reser v ed f or par ametr ic testing and should be connected to g round (lo w supply v oltage).
1- 398 nc no connection this pin is not connected to circuitr y within the de vice . ? nc no connection this pin is not connected to circuitr y within the de vice . pra pr obe a the probe a pin is used f or fpga diagnostics . function is controlled b y the mode pin. ? i/o this pin is used as an i/o only . it is not used f or diagnos- tic probe or de vice prog r amming functions on an mpga. prb pr obe b the probe b pin is used f or fpga diagnostics . function is controlled b y the mode pin. ? i/o this pin is used as an i/o only . it is not used f or diagnos- tic probe or de vice prog r amming functions on an mpga. qclka/b,c,d quadrant cloc k (input/output) (3200dx onl y) these f our pins are the quadr ant cloc k inputs . when not used as a register control signal, these pins can function as gener al pur pose i/o . ? no chang e if desired, ttl cloc k input signals ma y be mo v ed to an y mpga location. sdi serial data input ser ial data input f or diagnostic probe and de vice pro- g r amming. function is controlled b y the mode pin. ? i/o this pin is used as an i/o only . it is not used f or diagnos- tic probe or de vice prog r amming functions on an mpga. tck t est cloc k (3200dx onl y) cloc k signal to shift the jt a g data into the de vice . this pin functions as an i/o when the jt a g fuse is not pro- g r ammed ? no chang e tdi t est data in (3200dx onl y) ser ial data input or jt a g instr uctions and data. data is shifted in on the r ising edge of tclk. this pin functions as an i/o when the jt a g fuse is not prog r ammed. ? no chang e tdo t est data out (3200dx onl y) ser ial data output f or jt a g instr uctions and test data. this pin functions as an i/o when the jt a g fuse is not prog r ammed. ? no chang e tms t est mode select (3200dx onl y) ser ial data input f or jt a g test mode . data is shifted in on the r ising edge of tclk. this pin functions as an i/o when the jt a g fuse is not prog r ammed. ? no chang e v cc suppl y v olta g e high supply v oltage . ? v cc high supply v oltage . table 1 ? fpga-to-mpga pin cross- reference (continued) fpga pin description mpga pin description
1- 399 actel mask programmed gate arrays mpga architecture the actel mpga is built using a sea-of-gates architecture. a solid, regularly ordered array of transistors is overlaid with a multilevel metal interconnect. surrounding this logic core is an array of programmable power and i/o pads. separate grids provide power and ground supplies for the core logic and i/o cells. the highly dense structure of actel mpgas provides for a cost-effective solution while maintaining the high performance of each particular design. this architecture reduces die size for low cost while minimizing gate length and shortening routing paths for excellent system performance. the robust power supply grids provide high i/o current drive without sacrificing high noise immunity. since actel fpgas use a similar gate array architecture, design migration is a straightforward, simple process. because of the advanced technology employed by the mpga, the internal and external performance of each design is virtually assured to be preserved or improved after migration. to simplify migration further, the i/o pads are carefully arranged to allow fpga pin assignments to be directly transferred to the full line of mpga packages. for more information about the ease of design migration from actel fpgas to mpgas, see the application note designing for migration to actel mpgas. power dissipation the power dissipation for an actel mpga is composed of two parts: static power and active power. the static power is a product of the standby supply current (icc) and the dc supply voltage (vcc). specifications for icc and vcc are located in the electrical specifications section of this data sheet. the active power is a product of equivalent capacitance, square of the dc supply voltage, and average switching frequency of the circuit. it is expressed in the formula power ( m w) = c eq ? v cc 2 ? f where c eq is the equivalent capacitance in picofarads (pf) v cc is the dc supply voltage in volts (v) f is the switching frequency in megahertz (mhz) upon receipt of the design start checklist and associated materials, actel calculates the mpga active power dissipation for each design based on this formula. this calculation is immediately relayed to you so that you can update system power specifications accordingly. typically, power dissipation of an actel design is significantly lower for the mpga version versus the fpga version. timing characteristics the timing characteristics for actel mpga devices are consistent across family and device types. typical i/o buffer, internal logic cell, and internal routing delays are common to all mpga devices. the advanced technology of the devices ensures converted designs meet or exceed fpga performance. refer to the mpga timing model diagram and timing characteristics chart for detailed timing and delay estimates. timing derating timing derating factors due to temperature, voltage, and process variations are summarized in the following tables and graphs. use these derating factors to determine device performance at any particular condition within the electrical and environmental specifications. mpga devices are manufactured in a cmos process. therefore, device performance varies according to temperature, voltage, and process variations. minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing.
1- 400 timing derating factor, temperature and voltage timing derating factor for designs at typical temperature (t j = 25 c) and voltage (v cc = 5.0 v) industrial minim um maxim um (commercial minim um/maxim um speci? cation) x 0.85 1.07 (commercial maxim um speci? cation) x 0.86 note: this derating factor applies to all routing and propagation delays. v olta g e derating cur ve t emperature derating cur ve 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 4.5 4.75 5.0 5.25 5.5 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 -20 0 20 40 60 80 v cc (v olts) j unction t emper ature ( c) f actor f actor
1- 401 actel mask programmed gate arrays mpga timing model output buffer delays output dela ys internal dela ys input dela ys t iny = 2.0ns t ird2 = 0.3 ns t pd = 1.5 ns sequential logic module i/o module t rd1 = 0.2 ns t dhl = 5.5 ns f max = 167 mhz d q t co = 1.5 ns t sud = 1.5 ns t hd = 0.0 ns t rd4 = 0.7 ns t rd8 = 1.4 ns predicted routing dela ys t ckh = t ckl = 5.0 ns arr a y cloc k i/o module combinator ial logic module t dlh = 6.1 ns ? ? ? t o a c test loads (sho wn belo w) d e trib uff in v cc gnd 50% out v ol v oh 1.4 v t dlh 50% 1.4 v t dhl en v cc gnd 50% out v ol 1.4 v t enzl 50% 10% t enlz en v cc gnd 50% out gnd v oh 1.4 v t enzh 50% 90% t enhz v cc p ad
1- 402 ac test loads input buffer delays module delays sequential module timing characteristics flip-flops load 1 (used to measure pr opa gation dela y) load 2 (used to measure rising/falling edg es) 35 pf t o the output under test v cc gnd 35 pf t o the output under test r to v cc f or t plz /t pzl r to gnd f or t phz /t pzh r = 1 k w y inb uf in 0 v 1.4 v out gnd v cc 50% t iny 1. 4 v 50% t iny p ad s a b y s , a or b out gnd v cc 50% t pd out gnd gnd v cc 50% 50% 50% v cc 50% 50% t pd t pd t pd (p ositiv e edge tr iggered) d clk clr q d clk q clr t wclka t w asyn t hd t sud t a t wclka t co t clr
1- 403 actel mask programmed gate arrays sequential timing characteristics (continued) input buffer latches (3200dx only) output buffer latches (3200dx only) g p ad p ad clk d a t a g clk t inh clkb uf t insu t suext t hext ibdl d a t a d g t outsu t outh p ad obdlhs d g
1- 404 decode module timing (3200dx only) sram timing characteristic (3200dx only) aCg, h y t plh 50% v cc v cc t phl y a b c d e f g wrad [5:0] blken wen wclk rd ad [5:0] lew ren rclk rd [7:0] wd [7:0] wr ite p or t read p or t ram arr a y 32x8 or 64x4 (256 bits)
1- 405 actel mask programmed gate arrays dual-port sram timing waveforms sram write operation (3200dx only) note: identical timing for falling-edge clock. sram synchronous read operation (3200dx only) note: identical timing for falling-edge clock wclk wd[7:0] wrad[5:0] wen blken v alid v alid t rckhl t rckhl t wensu t bensu t wenh t benh t adsu t adh rclk ren rd ad[5:0] rd[7:0] old data v alid t rckhl t rckhl t renh t rco t adh t doh t adsu ne w data t rensu
1- 406 sram asynchronous read operationtype 1 (3200dx only) ( (read ad dress contr olled) sram asynchronous read operationtype 2 (3200dx only) (write ad dress contr olled) ren rd ad[5:0] rd[7:0] data 1 t rd ad v t renha t doh addr2 addr1 data 2 t rensu a (data 2 in hold state) t rpd wen wd[7:0] wclk rd[7:0] old data v alid t renh t wenh t rpd t wensu ne w data t doh t adsu wrad[5:0] blken ren t adh
1- 407 actel mask programmed gate arrays mpga timing characteristics (worst-case commercial conditions, v cc = 4.75 v, t j = 70 c) preliminar y inf ormation logic module pr opa gation dela ys p arameter description min. max. units t pd inter nal arr a y module 1.5 ns t co sequential cloc k to q 1.5 ns t clr asynchronous clear to q 1.5 ns predicted routing dela ys 1 t rd1 fo=1 routing dela y 0.2 ns t rd2 fo=2 routing dela y 0.3 ns t rd3 fo=3 routing dela y 0.5 ns t rd4 fo=4 routing dela y 0.7 ns t rd8 fo=8 routing dela y 1.4 ns logic module sequential timing t sud flip-flop data input setup 1.5 ns t hd flip-flop data input hold 0.0 ns t sud latch data input setup 1.5 ns t hd latch data input hold 0.0 ns t w asyn asynchronous pulse width 2.0 ns t wclka flip-flop cloc k pulse width 2.0 ns t a flip-flop cloc k input p er iod 8.0 ns f max flip-flop cloc k f requency 125 mhz i/o module input pr opa gation dela y t iny input data p ad to y 2.0 ns predicted input routing dela ys 1 t ird1 fo=1 routing dela y 0.2 ns t ird2 fo=2 routing dela y 0.3 ns t ird3 fo=3 routing dela y 0.5 ns t ird4 fo=4 routing dela y 0.7 ns t ird8 fo=8 routing dela y 1.4 ns note: 1. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. postroute timing analysis or simulation is required to determine actual worst-case performance. postroute timing is based on actual routing delay measurements performed on the device prior to shipment.
1- 408 mpga timing characteristics (continued) (worst-case commercial conditions) preliminar y inf ormation i/o module C ttl output timing 1 p arameter description min. max. units t dhl data to p ad, high to lo w 6.8 ns t dlh data to p ad, lo w to high 3.9 ns t enzh enab le to p ad, z to high 4.5 ns t enzl enab le to p ad, z to lo w 6.8 ns t enhz enab le to p ad, high to z 3.8 ns t enlz enab le to p ad, lo w to z 2.0 ns d tlh delta lo w to high 0.05 ns/pf d thl delta high to lo w 0.09 ns/pf i/o module C cmos output timing 1 t dhl data to p ad, high to lo w 5.5 ns t dlh data to p ad, lo w to high 6.1 ns t enzh enab le to p ad, z to high 6.7 ns t enzl enab le to p ad, z to lo w 5.6 ns t enhz enab le to p ad, high to z 3.8 ns t enlz enab le to p ad, lo w to z 2.0 ns d tlh delta lo w to high 0.09 ns/pf d thl delta high to lo w 0.07 ns/pf global cloc k netw orks (f or f anout = 1000) t ckh input lo w to high 5.0 ns t ckl input high to lo w 5.0 ns t pwh min. pulse width high 2.9 ns t pwl min. pulse width lo w 2.9 ns t cksw maxim um sk e w 0.4 ns t p minim um p er iod 6.0 ns f max maxim um f requency 167 mhz note: 1. delays based on 35pf loading.

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